Principal CPU Micro-Architect



Position Type: Full Time



Experience: 15-30 Years



Level: Principal/Senior Leadership




About the Role: We are seeking an exceptional Principal CPU Micro-Architect to join our advanced processor design team. This is a senior technical leadership position for an accomplished professional who will drive the architecture and design of next-generation high-performance processors.


Position Overview



As a Principal CPU Micro-Architect, you will be at the forefront of processor innovation, leading the definition, design, and optimization of cutting-edge CPU microarchitectures. This role demands deep technical expertise combined with strategic thinking to shape the future of our processor roadmap. You will work on complex architectural challenges, mentor engineering teams, and collaborate with cross-functional groups to deliver industry-leading processor solutions that meet demanding performance, power, and area requirements.


Key Responsibilities


Architecture Definition and Innovation

• Lead the definition and specification of CPU microarchitecture for next-generation processors, including pipeline organization, execution units, cache hierarchies, and memory subsystems


• Drive architectural innovation in areas such as branch prediction, instruction fetch and decode, out-of-order execution, register renaming, load-store units, and retirement mechanisms


• Develop and evaluate novel microarchitectural features to improve performance, power efficiency, and security across diverse workloads


• Create comprehensive architectural specifications and documentation that serve as the foundation for RTL design teams


• Define and optimize instruction set architecture (ISA) implementations for ARMv8/v9, Intel x86_64,

• MSc or PhD in Computer Science, Electrical Engineering, or equivalent industry experience


• Hands-on CPU microarchitecture experience on out-of-order cores


• Deep working knowledge of at least one major area: branch prediction, prefetching, OoO execution, memory subsystem, or cache coherence


• Proven experience with cycle-accurate simulators (gem5 or proprietary equivalents)


• Strong workload analysis skills - performance counter methodology, top-down analysis, trace inspection


• Proficient in C++ and Python for modelling, analysis tooling, and automation


• Familiarity with ARMv8/v9, Intel x86_64 or RISC-V ISA at the microarchitectural level

• PhD in computer architecture with publications at ISCA, MICRO, HPCA, or ASPLOS


• Experience with dynamic language runtimes (V8, SpiderMonkey, ArkCompiler) and JIT/AOT code generation


• Exposure to AI/ML inference workloads on CPU and CPU-NPU co-design


• Track record of features that shipped in production silicon


• Familiarity with LLM-driven design exploration or agentic optimisation flows